SQNR Improvement of Incremental Zoom ADCs with Raised-Order CoI Filter and Dither Injection

This paper presents a behavior-level approach to improve the SQNR of incremental zoom ADCs with low hardware costs. The digital outputs of the L-th incremental zoom ΔΣ modulator are decimated using an (L+1)-th cascade-of-integrator (CoI) filter. The final quantization error is reduced through accumulating the original quantization error and then averaging. Moreover, the tonal component in the quantization error of zoom architectures is mitigated by injecting Gaussian dithering at the coarse SAR ADC input. Simulation results reveal that a dithered 2nd-order 5-bit incremental zoom ADC can achieve 114.5dB SQNR with a 3rd-order CoI decimation filter, showing a 7dB improvement over the architecture without this method. The resulting hardware overhead is only capacitors for dithering and DFFs in the digital filter, hardly raising any requirement for the analog circuit blocks.

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Publication Details

Published
2025-05-25
DOI
https://doi.org/10.1109/iscas56072.2025.11043297
Citations
1
Primary Topic
Analog and Mixed-Signal Circuit Design
Type
article
Field-Weighted Citation Impact
0.67

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article

SQNR Improvement of Incremental Zoom ADCs with Raised-Order CoI Filter and Dither Injection

Lingxin Meng, Menglian Zhao, Zhichao Tan
1 citations
Analog and Mixed-Signal Circuit Design
0.67
article

SQNR Improvement of Incremental Zoom ADCs with Raised-Order CoI Filter and Dither Injection

Lingxin Meng, Menglian Zhao, Zhichao Tan
article en
1 citations

Abstract

This paper presents a behavior-level approach to improve the SQNR of incremental zoom ADCs with low hardware costs. The digital outputs of the L-th incremental zoom ΔΣ modulator are decimated using an (L+1)-th cascade-of-integrator (CoI) filter. The final quantization error is reduced through accumulating the original quantization error and then averaging. Moreover, the tonal component in the quantization error of zoom architectures is mitigated by injecting Gaussian dithering at the coarse SAR ADC input. Simulation results reveal that a dithered 2nd-order 5-bit incremental zoom ADC can achieve 114.5dB SQNR with a 3rd-order CoI decimation filter, showing a 7dB improvement over the architecture without this method. The resulting hardware overhead is only capacitors for dithering and DFFs in the digital filter, hardly raising any requirement for the analog circuit blocks.

Zhejiang Province Institute of Architectural Design and Research (CN), Zhejiang University (CN)
National Natural Science Foundation of China
Openalex Percentile: Top 30%
Analog and Mixed-Signal Circuit Design
0.67
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SQNR Improvement of Incremental Zoom ADCs with Raised-Order CoI Filter and Dither Injection — Lingxin Meng, Menglian Zhao, et al. · (2025) | TGRS Research Map | TGRS