A Floating-Point SRAM-based CIM Macro with Asynchronous Normalization and Parallel Sorting Alignment

Floating-point computing-in-memory (FP-CIM) has a broader range of applications compared to integer CIM. However, FP-CIM can incur greater power, delay, and area overheads than integer CIM due to a more complex computational flow. In this paper, we introduce a new method for asynchronous exponent normalization and parallel mantissa alignment. This approach allows us to add exponents and find the maximum sum simultaneously. We also replace the traditional subtraction and shifting for mantissa alignment with a time-cycle lookup method, enabling FP-CIM to be achieved with lower delay, area, and power overheads. The macro is designed in the TSMC 28nm process, with a memory size of 6Kb, a layout area of 0.067mm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup>, and an area efficiency of 1.3TFLOPS/mm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup>. Simulation results show that the macro computational frequency and energy efficiency can reach 150MHz and 12.8TFLOPS/W, respectively at 900mV.