FPGA Accelerated Adaptive LDPC-based Quantum Error Correction by Bitwise Pipeline Parallelism

Quantum networks are at the forefront of next-generation communication technologies, providing unparalleled security by leveraging the fundamental properties of quantum mechanics. However, noise and interference adversely affect information sharing within quantum networks, causing quantum bit errors and diminishing the quality of quantum keys. To address this issue, high-speed quantum information error correction is necessitated and this work proposes an FPGA-accelerated error correction system based on low-density parity check (LDPC), incorporating algorithm-hardware co-optimizations. The proposed hardware architecture is applicable to generic LDPC soft decision algorithms and can adaptively select LDPC matrices with different code rates based on the quantum bit error rates. Experiment results demonstrate that the system exhibits high performance in error correction acceleration, achieving a throughput of 728 Mbps and up-to 9.4× speedup compared to existing FPGA-based LDPC error correction implementations.