Efficient Floating-Point Divider based on Hybrid Cubic-Quadratic Goldschmidt Algorithm

This paper presents an efficient floating-point divider based on the Hybrid Convergent Goldschmidt algorithm, which combines Goldschmidt iterative methods with cubic and quadratic convergence rates. This approach accelerates the convergence of initial errors, supports multiple precision levels, and reduces the precision requirements for the initial lookup table.Additionally, we significantly reduce the multiplier bitwidth during the iteration process by introducing a novel analysis of error convergence, accumulation characteristics, and variable ranges. To demonstrate this, we present a floating-point divider design based on the proposed method, which has been validated with 100 billion random vector tests, confirming the accuracy and robustness of the error analysis. Circuit implementation shows that the architecture achieves a substantial reduction in latency compared to previous designs, while maintaining high operational frequency and occupying less silicon area.

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Publication Details

Published
2025-05-25
DOI
https://doi.org/10.1109/iscas56072.2025.11043381
Primary Topic
PAPR reduction in OFDM
Type
article
Field-Weighted Citation Impact
0.00

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article

Efficient Floating-Point Divider based on Hybrid Cubic-Quadratic Goldschmidt Algorithm

Yuan Wang, Liangtao Dai, Haocheng Zhu, Xin Lou
PAPR reduction in OFDM
article

Efficient Floating-Point Divider based on Hybrid Cubic-Quadratic Goldschmidt Algorithm

Yuan Wang, Liangtao Dai, Haocheng Zhu, Xin Lou
article en

Abstract

This paper presents an efficient floating-point divider based on the Hybrid Convergent Goldschmidt algorithm, which combines Goldschmidt iterative methods with cubic and quadratic convergence rates. This approach accelerates the convergence of initial errors, supports multiple precision levels, and reduces the precision requirements for the initial lookup table.Additionally, we significantly reduce the multiplier bitwidth during the iteration process by introducing a novel analysis of error convergence, accumulation characteristics, and variable ranges. To demonstrate this, we present a floating-point divider design based on the proposed method, which has been validated with 100 billion random vector tests, confirming the accuracy and robustness of the error analysis. Circuit implementation shows that the architecture achieves a substantial reduction in latency compared to previous designs, while maintaining high operational frequency and occupying less silicon area.

Nanyang Technological University (SG), ShanghaiTech University (CN)
National Key Research and Development Program of China
Openalex Percentile: Top 87%
PAPR reduction in OFDM
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