Characterization of Stacked PV Cell Configurations in a Deep N-Well 65nm CMOS Technology

The selection of a suitable photovoltaic (PV) design for emerging energy harvesting applications remains challenging, as PV cell performance is highly dependent on design variables and environmental setup. These factors vary widely across existing studies, making direct comparisons complex and increasing uncertainty in predicting expected PV cell output characteristics for a given use case. To address this, our paper presents a comparison of various on-chip PV cell configurations, implemented using a 0.6mm x 0.6mm test chip realized in 65nm deep-nwell (DNW) CMOS technology. The experimental results demonstrate that, depending on diode arrangements, separate configurations achieve a maximum open-circuit voltage of 0.54V and a peak power density of 1.18 µW/mm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> at 20 klux illumination. This characterization work, therefore, enables designers to select an optimal configuration tailored to specific application scenarios.