DyLock: A Dynamic Key-based SAT and Structural Attacks Resilient Low-overhead Logic Locking

Recent advances in secure integrated circuit design with logic locking have identified structural and algorithmic vulnerabilities that compromise various defenses to retrieve the correct secret key. Most defense techniques use static keys and incur a relatively high design overhead. This paper presents a novel dynamic key-based logic locking technique (DyLock) to improve resilience against Boolean satisfiability (SAT) and structural attacks while maintaining low design overhead. DyLock employs a nonlinear substitution-based key generator and counter-based architecture to produce a dynamic key sequence from static key bits. It significantly increases the SAT solver’s key search space and presents low key prediction accuracy for SWEEP and SCOPE attacks. An experimental evaluation using the ISCAS’85, ISCAS’89, and ITC’99 benchmark with 16/32/64-bit keys, DyLock demonstrates reduced area and power overheads compared to existing attack-resistant locking schemes. The proposed technique offers a balance between overhead and security, strengthening the locking against algorithmic and structural attacks.