A Wideband Open-Loop Residue Amplifier for a 7-bit 10GS/s Two-Step Flash ADC in 22nm SOI CMOS Process

This paper presents a residue amplifier scheme consisting of a high-speed current-steering (CS) digital-to-analog converter (DAC) and a wideband active back-biased open-loop amplifier. The proposed current-summing residue amplifier scheme utilizes a 4-bit CS-DAC converting the first-stage sub-ADC output, which is subtracted from the resampled input current generated by the transconductance of the amplifier providing a nominal voltage gain of 8. The residue amplifier takes advantage of several measures to enhance output bandwidth, gain and linearity, which are inductive shunt peaking, source degeneration and active body biasing. The proposed 4-bit DAC and residue amplifier are designed for an energy-efficient 10 GS/s 7-bit two-step flash ADC. The proposed ADC achieves an ENOB and SFDR of 6.57/5.83 bit and 48/47.7 dBc at Nyquist frequency respectively, at a sampling rate of 5/10 GS/s. The DAC and residue amplifier are realized in the 22nm SOI CMOS process and consume 10.8 mW and 39.3 mW from a single 1.2 V power supply.