Design of a Single-Event Upset Tolerant Low-Power Double-Tail Comparator

Comparators have been optimized for quick decision-making and reduction of dynamic power consumption through years of research by incorporating strong positive feedback latches. However, these advancements can make double-tail dynamic comparators more susceptible to single-event effects (SEEs). In this work, we present a new comparator design that is hardened against these radiation effects. The proposed design is a modified version of a low-voltage, low-power double-tail comparator, designed in a 180 nm technology node, and it can achieve high levels of SEE tolerance with an acceptable degree of trade-off in area, delay, and power consumption. The proposed comparator is shown to have superior SEE tolerance compared to a radiation-hardened conventional double-tail comparator with a similar electrical performance designed in the same technology node, and the proposed design’s functionality is proven by post-layout simulations across extreme simulation corners, combining process corners with temperature and supply voltage variations.