Design and Implementation of an Energy-Efficient Detector for Uplink Cell-Free MIMO Networks

This paper presents the design and hardware implementation of an energy-efficient data detector for uplink cell-free (CF) MIMO networks. The design is based on the DMPACT CF MIMO detection algorithm proposed in [7], which beats other CF detection methods in terms of detection performance and computational complexity. We have proposed several novel techniques in this detector, including eigenvalue decomposition, CORDIC algorithms, and fast inverse square root calculations, to compute the Mahalanobis distances, reducing multiplication complexity by 81%. Additionally, Gaussian approximation was further proposed for complexity optimization. The final hardware design incorporates circuit sharing, outcome reuse, and pipelining to enhance circuit performance. Finally, synthesized using the 28nm CMOS technology, the proposed multi-core hardware operates at 667 MHz and achieves a 10.67 nJ/bit energy efficiency, beating the single-core approach by at least 16%.

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Publication Details

Published
2025-05-25
DOI
https://doi.org/10.1109/iscas56072.2025.11044201
Primary Topic
Advanced MIMO Systems Optimization
Type
article
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article

Design and Implementation of an Energy-Efficient Detector for Uplink Cell-Free MIMO Networks

Ti-Yu Chen, Tzi‐Dar Chiueh
Advanced MIMO Systems Optimization
article

Design and Implementation of an Energy-Efficient Detector for Uplink Cell-Free MIMO Networks

Ti-Yu Chen, Tzi‐Dar Chiueh
article en

Abstract

This paper presents the design and hardware implementation of an energy-efficient data detector for uplink cell-free (CF) MIMO networks. The design is based on the DMPACT CF MIMO detection algorithm proposed in [7], which beats other CF detection methods in terms of detection performance and computational complexity. We have proposed several novel techniques in this detector, including eigenvalue decomposition, CORDIC algorithms, and fast inverse square root calculations, to compute the Mahalanobis distances, reducing multiplication complexity by 81%. Additionally, Gaussian approximation was further proposed for complexity optimization. The final hardware design incorporates circuit sharing, outcome reuse, and pipelining to enhance circuit performance. Finally, synthesized using the 28nm CMOS technology, the proposed multi-core hardware operates at 667 MHz and achieves a 10.67 nJ/bit energy efficiency, beating the single-core approach by at least 16%.

National Taiwan University (TW)
Affordable and clean energy
Openalex Percentile: Top 87%
Advanced MIMO Systems Optimization
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Design and Implementation of an Energy-Efficient Detector for Uplink Cell-Free MIMO Networks — Ti-Yu Chen, Tzi‐Dar Chiueh · (2025) | TGRS Research Map | TGRS