RS-CIM: Area-efficient Compute-in-Memory with R-DAC & SAR Hybrid ADC

Analog computing offers higher energy efficiency compared to digital, making it suitable for low-power applications. However, the area overhead of digital-to-analog converter (DAC) and analog-to-digital converter (ADC) reduces area efficiency, either by requiring an analog MUX or by lowering cell array density. To solve this problem, we propose a high-area efficiency analog compute-in-memory structure consisting of a 7T SRAM-based digital-to-time converter with clock multiplication and a hybrid ADC structure of a resistor-DAC and SAR ADC. Compared to conventional SAR ADCs and flash ADCs, the number of capacitors and comparators was reduced by 87.5% and 93.3%, respectively. As a result, we achieved 247.7 TOPS/W and 6.498 TOPS/mm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> when scaling down to 28 nm process.