Fast and Accurate Analysis of Power Distribution Network Impedance for DRAM Design

In DRAM circuits, package and on-chip power distribution network (PDN) should be analyzed as a whole, necessitating impedance analysis. Circuit-level simulation at a number of sample frequency points is a standard practice but is very time consuming. We propose a multi-layer perceptron (MLP) machine learning model for quick prediction of the resonant frequency of each VDD-VSS node pair. Such resonant frequencies are clustered; frequency points for impedance analysis are sampled, densely around clustered resonant frequencies and sparsely outside of clusters. Experimental results show that our method reduces the number of frequency points by 91.6% and the runtime of impedance analysis by 90.4% compared to standard practice, with less than 3% error in predicted maximum impedance.