A Digital Reference-less CDR Achieving Bandwidth Down to 4 Hz and Locking Time Less Than 1000 Cycles Based on a Self-Adaptive PFD for Medical Implant Applications

The wireless clock and data may experience significant discontinuation in battery-less medical implant applications. The rise of closed-loop treatment requires the communication link to set up swiftly. To address these issues, a single-loop digital clock and data recovery (CDR) circuit based on a self-adaptive bang-bang phase and frequency detector (PFD) is proposed. For a data rate at 5 kbps, the CDR features a 4-Hz loop-bandwidth and fast locking less than 1000 cycles. A wide frequency capture range from −63% to +56% has been achieved without the need for crystal references. The CDR is realized in a digital design eliminating any off-chip components. It occupies 0.027 mm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and consumes a power consumption of 4.89 μW in a 180-nm CMOS technology. The compact form factor especially favors size-constraint medical implant applications.