A Low-Power Cyclic ADC with Capacitive Degeneration Amplifier and Charge Mode Operation

This paper presents a low-power 10-bit cyclic ADC that replaces the conventional high-power operational amplifier with a capacitive degeneration amplifier and charge mode operations for amplification. To enhance linearity during cyclic operation, dynamic switching is employed to mitigate the effects of drain parasitic charges. The ADC utilizes two comparators to implement a 1.5-bit-per-cycle algorithm, improving tolerance to comparator offset. A pre-sampling phase allows for charge sharing between pre-sampling and sampling capacitors, effectively compressing the input signal to fit within the range allowed by the capacitive degeneration amplifier, achieving a ±3V input voltage range. The ADC is implemented in a standard 180 nm CMOS process, and its performance is verified by simulation. At a sampling rate of 55 kS/s, it achieves an SNDR of 51.3 dB and an SFDR of 54.4 dB, yielding an ENOB of 8.23 bits. The ADC consumes only 6.03 μW at a 3.3 V supply.