A 22-nm Surface Code Decoder Using Greedy Algorithm

To realize a fault-tolerant quantum computer, a quantum error decoder that can handle a large number of qubits with high speed is required. This paper demonstrates an ASIC implementation of a quantum error decoder based on a greedy algorithm. The simple algorithm and microarchitecture enable a low-power and compact design. A test chip is fabricated using 22-nm CMOS technology, and its operation is verified through empirical evaluation.