A bidirectional frequency detector independent of input transition density for a wide-tuning range applications

This paper presents a dual-loop reference-less Clock and Data Recovery (CDR) architecture implemented in TSMC 28nm CMOS process for PCIe Gen4 application. A novel frequency detector (FD) with a wide frequency acquisition range is presented, which avoids harmonic locking issues and is independent of input transition density. The FD demonstrates rapid locking capabilities, securing synchronization with Pseudo-Random Binary Sequences (PRBS7 and PRBS31) data patterns. The locking time from PCIe Gen1 (2.5Gbps) to PCIe Gen4 (16Gbps) is less than 5us. The CDR achieves a power consumption of less than 2mW with a supply voltage of 0.9V.