Analysis and Modeling of Helical Ladder Switched-Capacitor DC-DC Converters for Fractional VCRs

This paper presents an analytical study and modeling of the Helical ladder switched capacitor converters (HLSC). The higher output impedance (R<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OUT</inf>) problem in the conventional ladder switched capacitor converter (CLSC) is addressed in the HLSC by identifying the large charge carrying flying capacitors of CLSC and reconfiguring them to reduce the charge flow. A systematic process is proposed to develop an HLSC architecture for any given voltage conversion ratios (VCR) using its equivalent CLSC architecture. As the switched capacitor converter (SCC) performance mainly depends on the R<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OUT</inf>, analytical models are developed to calculate the R<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OUT</inf> using switching frequency (f<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">SW</inf>), total flying capacitance (C<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">tot</inf>), and load current (I<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">L</inf>) for an n-stage HLSC and CLSC. From these models, the variation of charge sharing loss and parasitic capacitance loss, and their impact on the efficiency (η) and output voltage (V<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OUT</inf>) is analyzed across all the VCRs. The comparison between CLSC and HLSC results shows that the HLSC has superior performance over CLSC. The developed models are useful for comparing the different performance metrics of various SCC topologies.