An SRAM-Based Digital Compute-in-Memory Macro with Dual-Bit Input Data Sparsification and Restructuring for Energy-Efficient MAC

SRAM-based digital computing-in-memory (CIM) provides a low-power, high-precision method for multiply-and-accumulate (MAC) operations. However, input data with a high toggle rate and low sparsity will significantly increase the energy consumption of digital CIMs. This work presents an input-transforming and weight-precomputation (ITWP) SRAM-based digital CIM macro. Two strategies involving input sparsification and input restructuring are proposed to transform the dual-bit input data, resulting in higher sparsity and lower toggle rate. The sum of the weights is precomputed to correct the partial sum (PSUM) of the sparsified input data. A 13T-based hybrid SRAM CIM unit (HSCU) and a split adder tree (SAT) are proposed to compute on the restructured two input sets with different sparsity levels, leading to a higher throughput and energy efficiency. Finally, the ITWP CIM macro is implemented in a 28 nm process and achieves a peak throughput of 0.935 TOPS and an energy efficiency of 20.08-33.78 TOPS/W with signed 8b input and weight. Compared to the conventional bit-serial CIM macro, the ITWP CIM macro is demonstrated to increase the energy efficiency to 1.42x and up to 3.04x.