ASP: A daptive Sparse LUT-based Bit-Slice Accelerator for Efficient CNN Inference

Recent advances in convolutional neural network (CNN) accelerators have leveraged data sparsity, significantly enhancing energy efficiency in resource- and energy-constrained hardware platforms. However, fully exploiting data sparsity and further enhancing energy efficiency require the deployment of specialized hardware accelerators. In this work, we present a bit-slice accelerator that integrates an LUT-based multiplier and a bit manipulation unit to achieve efficient resource utilization and low-latency multi-bit-width operations. Furthermore, the bit-slice processing element (PE) and dynamic PE array utilize adaptive subdivision for irregular matrices, optimizing data handling across varying levels of sparsity. Our synthesized RTL implementation demonstrates a significant improvement in hardware utilization, achieving a throughput of 66.23 GOPS/W on AlexNet and 61.13 GOPS/W on VGG16. This design achieves 2.05x higher energy efficiency and 2.75x lower latency compared to state-of-the-art designs, outperforming them on both the AlexNet and VGG16 benchmarks.