Quantization Noise Cancellation Through Modelling of Non-Linearities in Sigma Delta Modulators

The linearity of Sigma Delta Modulators (SDMs) is evaluated performing a Fourier Transform of the output bitstream. The presence of quantization noise complicates this task: many samples and lengthy simulations are needed to lower this noise floor and evaluate the signal harmonics. We present here a method to estimate the quantization noise, remove it from the SDM bitstream, and enable the reduction of the samples needed to evaluate the SDM linearity. By applying the proposed technique to a Simulink<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">®</sup> model of a 4<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sup>-order SDM, the accuracy of the linearity estimation is kept unchanged using 5000x less bitstream samples. This method enables a significant reduction of SDM verification time that in turn can be used to improve the statistical coverage of design over parameter variability.

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Published
2025-05-25
DOI
https://doi.org/10.1109/iscas56072.2025.11044157
Citations
1
Primary Topic
Analog and Mixed-Signal Circuit Design
Type
article
Field-Weighted Citation Impact
0.67

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Quantization Noise Cancellation Through Modelling of Non-Linearities in Sigma Delta Modulators

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Quantization Noise Cancellation Through Modelling of Non-Linearities in Sigma Delta Modulators

Stijn Ringeling, Eugenio Cantatore, Lucien J. Breems, Marco Fattori, Shagun Bajoria, Robert J. Rutten
article en
1 citations

Abstract

The linearity of Sigma Delta Modulators (SDMs) is evaluated performing a Fourier Transform of the output bitstream. The presence of quantization noise complicates this task: many samples and lengthy simulations are needed to lower this noise floor and evaluate the signal harmonics. We present here a method to estimate the quantization noise, remove it from the SDM bitstream, and enable the reduction of the samples needed to evaluate the SDM linearity. By applying the proposed technique to a Simulink<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">®</sup> model of a 4<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sup>-order SDM, the accuracy of the linearity estimation is kept unchanged using 5000x less bitstream samples. This method enables a significant reduction of SDM verification time that in turn can be used to improve the statistical coverage of design over parameter variability.

NXP (Netherlands) (NL), Eindhoven University of Technology (NL)
NXP Semiconductors, Ministry of Economic Affairs
Affordable and clean energy
Openalex Percentile: Top 30%
Analog and Mixed-Signal Circuit Design
0.67
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