Efficient Multiple-Precision Floating-Point Multiply-Add Architecture for Deep Learning Applications

To fully exploit the potential of parallel computing while minimizing hardware costs, floating-point multiply-add (FMA) units that support multiple precisions are widely used in deep learning. However, achieving a balance between accuracy, performance, and hardware overhead remains a significant challenge. This paper presents a unified multiple-precision floating-point FMA architecture that supports four precision formats: single-precision (SP), Bfloat16 (BF16), TensorFloat32+ (TF32+), and INT8. The proposed architecture allows for the parallel execution of nine BF16 FMA operations, two TF32+ FMA operations, one SP FMA operation, or nine INT8 multiply-add (MA) operations. Through careful data format selection and an optimized architectural design, the architecture achieves multiplier utilization rates of 100%, 88.9%, 100%, and 100% for the four precision modes, respectively, with all multipliers operating at full bit width. Compared to state-of-the-art multiple-precision FMA designs, this architecture delivers over nine times the BF16 throughput while increasing the area by only 49%. The flexible data format configuration makes the proposed architecture suitable for a wide range of deep learning applications.