An Area-Efficient VLSI Architecture for Parallel Jacobi-based Eigenvalue Decomposition with Inherent Eigenvalue Sorting

The Jacobi algorithm is widely used for eigen-value decomposition (EVD), and its parallel implementation is preferred in real-time applications which demand low latency. However, the parallel implementations are computationally expensive in terms of area overhead. In this paper, we propose an area-efficient implementation of the parallel Jacobi algorithm without compromising the latency and accuracy. Additionally, the proposed architecture is inherently self-sorting, thereby avoiding the need for a dedicated hardware to sort the eigenvalues. ASIC synthesis results of the designed architecture show that the proposed method achieves a 23.4% reduction in area over the state-of-the-art implementation, with no significant impact on latency. FPGA implementation results also demonstrate optimized hardware utilization.