Two-step ADC with Self-Successive Doubling Algorithm for High-Speed CIS

This paper presents a high-speed CMOS image sensor (CIS) using a two-step analog-to-digital converter (ADC) that applies the self-successive doubling (SSD) algorithm. The proposed readout circuit uses a successive approximation register (SAR) ADC to implement a high-speed CIS and addresses the area requirements of the SAR ADC by employing an SSD circuit. The SSD circuit has a structure similar to conventional analog correlated double sampling (CDS) circuits, which simultaneously perform CDS and ADC operations. The proposed high-speed two-step ADC uses SSD logic for MSB and SAR ADC for LSB, thereby reducing the capacitance area by about 96.8% compared to a conventional 12-bit SAR-ADC. The proposed circuit is fabricated using a 180 nm process, with a total power consumption of 7.54 mW and a frame rate of 1190 fps.