A Power-Efficient Architecture for LES Solving and ∆MV Calculation of VVC Affine Prediction

The increasing demand for video content has created a need for more efficient video compression techniques and the Versatile Video Coding (VVC) standard introduces several techniques to reach this goal. One key innovation in VVC is affine prediction, which gives more flexibility in inter-frame prediction by using multiple motion vectors for motion representation. However, its processing demands significant computational effort, boosting the use of dedicated hardware accelerators to enable real-time processing, mainly when focusing on mobile devices. This work introduces a pipelined and parallelized hardware design for the Linear Equation System (LES) solving and the ∆MV calculation, both essential steps in the search for affine motion vectors. The proposed architecture can generate new ∆MV values every three clock cycles and can process UHD 4K@60fps videos dissipating 47.32mW, with a negligible coding efficiency impact of 0.006%. These results outperform all related works in the literature, achieving twice the throughput, 84.2% lower power dissipation, and five times better coding efficiency.