Precision-Factored Systolic Arrays: Balancing Accuracy and Efficiency in Floating-Point Computations for CNNs

Approximate computing involves trading precision for improved performance in applications where exact accuracy is not essential. This study explores approximate computing in floating-point multipliers for Weight Stationary Systolic Arrays, examining IEEE 754 (FP32), TensorFloat-32 (TF32), and Brain Floating point (BF16) formats. We combine column truncation with positive and negative compressors to optimize computation efficiency versus accuracy. Using NSGA-II algorithm to explore design configurations, we achieve significant hardware improvements while maintaining high output quality. Testing across image processing kernels and CNN layers shows improvements of up to 28% in critical path delay, 69% in silicon footprint reduction, and 66% in power savings, while preserving high structural similarity (SSIM) values. The approach demonstrates that strategic approximation in floating-point multiplier design can substantially enhance hardware accelerator efficiency in error-tolerant applications. By balancing precision sacrifices against performance gains, we establish a viable method for optimizing hardware resources in modern computing architectures.