A Reference Double-Sampling PLL-Based Eight Phase Clock Generator Achieving 0.18mW/GHz/phase and -251.9dB FOMJitter-N

A reference double-sampling phase-locked-loop-based (RDSPLL-based) multi-phase clock generator (MPCG) for DDR PHY is presented. The reference double-sampling architecture is utilized to achieve low phase noise. A CDAC-embedded voltage offset calibration is proposed to reduce jitter and reference spur, and a CMP-ADC hybrid phase detector is adopted to accelerate the locking process. Fabricated in 65nm, the proposed MPCG achieves better than 1° phase accuracy with a 100MHz reference clock. The reference spur is reduced from -56dBc to -80dBc and the locking time is reduced from 10.5us to 1.6us. The measured RMS jitter is 674fs at 2.4GHz with 3.43mW, yielding the FOM<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Jitter-N</inf> of -251.9dB.