Hardware Implementation of Modified Noisy Gradient Descent Bit-Flipping Decoders

Recently, modified noisy gradient descent bit flipping (MNGDBF) algorithms have been proposed to eliminate the Gaussian random generators required in the original noisy gradient descent bit flipping (NGDBF) algorithm for the decoding of low-density parity-check (LDPC) codes. In this paper, a platform has been established for the hardware implementation of the LDPC encoder, the Gaussian noise channel generator and the decoder using MNGDBF decoding algorithms based on the use of field programmable gate array (FPGA). With 6-bit quantization, results show that the error performance achieved by hardware experiments is similar to that obtained by floating-point computer simulations. Moreover, we propose a new MNGDBF algorithm, in which the flipping condition is determined with the help of the summation of all inversion functions. Experimental results show that the proposed algorithm has superior performance than the original MNGDBF algorithm.