Live Demonstration: VVC Intra-Coding Visualizer
This paper presents a live demonstrator that is designed to visualize the encoding process of uvg266 VVC open-source intra encoder. The proposed visualizer provides real-time insights into the decision-making process of uvg266 by illustrating chosen block structures, modes, transforms, and parallelization strategies. The tool also facilitates interactive analysis through a user-friendly interface that allows users to dynamically adjust encoding tools and parameters on the fly. Researchers, developers, and students can use the tool to enhance their understanding of VVC coding flow and to support their optimization and educational efforts.
Authors
- Jarno Vanne (ORCID: https://orcid.org/0000-0002-7944-1938)
- Alexandre Mercat (ORCID: https://orcid.org/0000-0003-2211-970X)
- Joose Sainio (ORCID: https://orcid.org/0000-0002-3394-1363)
Institutions
- Tampere University (FI)
Publication Details
- Published
- 2025-05-25
- DOI
- https://doi.org/10.1109/iscas56072.2025.11043749
- Primary Topic
- Analog and Mixed-Signal Circuit Design
- Type
- article
- Field-Weighted Citation Impact
- 0.00
Funders
- Business Finland