A 65nm 100MS/s-400MS/s Multi-Column SAR/SS ADC with Reconfigurable 2-8 Bit Resolution for Optical and In-memory Computing

Computing-in-Memory (CIM) architecture effectively reduces power consumption caused by data movement between analog computing elements and memory. Optoelectronic computing offers a promising alternative to traditional analog computing by bypassing the energy-bandwidth tradeoff and reducing latency. In analog computing architectures, analog-to-digital converters (ADCs) are essential for quantizing column-parallel computing results. However, ADCs with fixed resolution can result in unnecessary power consumption during low-resolution requirements. In this paper, we propose a hybrid ADC with a configurable resolution from 2 to 8-bit. The ADC integrates successive approximation register (SAR) and single-slope (SS) circuits to minimize the area and power consumption. The proposed ADC architecture was fabricated in 65nm CMOS process with a 1 V power supply. The prototype occupies an area of 177μm × 11μm and consumes 238μW in the 8-bit conversion mode. Measured results show that the ADC achieves an effective number of bits (ENOB) of 7.35 and a Walden figure of merit (FoMw)of 14.6 fJ/conv.