DPAcc: An FPGA-based Differential Privacy Acceleration Framework

In the data-driven era, privacy protection has become a critical concern. Differential privacy is an effective technique that incorporates random noise during data processing to ensure that alterations to individual data points do not significantly affect overall outputs. However, the additional operations required by differential privacy can result in prolonged training times and degraded model performance. This work proposes DPAcc, an FPGA-based acceleration framework for differential privacy that utilizes hardware implementation to decrease training time. The designed FPGA module efficiently executes clipping and noise addition operations, significantly reducing the overhead compared to standard training. Experimental results demonstrate that DPAcc improves training efficiency across multiple models, achieving up to 2× speedup compared to standard differential privacy training methods.

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Publication Details

Published
2025-05-25
DOI
https://doi.org/10.1109/iscas56072.2025.11044265
Primary Topic
Physical Unclonable Functions (PUFs) and Hardware Security
Type
article
Field-Weighted Citation Impact
0.00

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article

DPAcc: An FPGA-based Differential Privacy Acceleration Framework

Yifei Tian, Xiaobai Chen, Jieming Yin, Yuxiang Wang et al.
Physical Unclonable Functions (PUFs) and Hardware Security
article

DPAcc: An FPGA-based Differential Privacy Acceleration Framework

Yifei Tian, Xiaobai Chen, Jieming Yin, Yuxiang Wang, Pengyang Li, D. Ao
article en

Abstract

In the data-driven era, privacy protection has become a critical concern. Differential privacy is an effective technique that incorporates random noise during data processing to ensure that alterations to individual data points do not significantly affect overall outputs. However, the additional operations required by differential privacy can result in prolonged training times and degraded model performance. This work proposes DPAcc, an FPGA-based acceleration framework for differential privacy that utilizes hardware implementation to decrease training time. The designed FPGA module efficiently executes clipping and noise addition operations, significantly reducing the overhead compared to standard training. Experimental results demonstrate that DPAcc improves training efficiency across multiple models, achieving up to 2× speedup compared to standard differential privacy training methods.

Nanjing University of Posts and Telecommunications (CN)
Nature
Affordable and clean energy
Openalex Percentile: Top 85%
Physical Unclonable Functions (PUFs) and Hardware Security
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