A Mutually Coupled High Speed Multi-Phase Clock Distribution Scheme for Improved Signal Integrity

An efficient clock distribution scheme is very important in high-speed interface designs as it directly impacts power, performance and area (PPA) of overall high-speed link. Ever increasing interface speed has resulted in multi-phase clock distributions (e.g., half-rate, quarter-rate architecture) becoming a reality over single / complementary phase clock distribution for performance reasons. Conventional techniques of clock distribution often involve distributing multi-phase clocks in pairs of complementary clock phases with proper shields around these phases to avoid coupling with other non-complementary clock phases of multi-phase clock distribution. However, these schemes suffer heavily when speeds/datarates and routing length of clock distribution increase. A mutually coupled multi-phase clock distribution scheme is proposed that overcomes signal integrity issues observed in the conventional multi-phase clock distribution scheme. Two schemes, correct by design (CD) and correct by layout (CL) are, proposed to boost performance over conventional methods. Mutual coupling is effectively used between N-phase clocks and matched clocks are distributed with minimal/zero power overhead. Implemented in 7nm FinFET technology, the proposed schemes improve clock swings by ~4.75%-8%, random jitter (RJ) by ~4%-10%, rise/fall times by 10%-23% and achieves perfect matching between N phases of the clock.