Optimized and Reconfigurable Hardware Design for ASCON AEAD and Hash Standards

NIST has finalized LWC standardization process by selecting ASCON as the new standard. ASCON is a versatile algorithm supporting two primary functions: AEAD and HASH. The standard includes three AEAD variants "ASCON-128, ASCON-128a, ASCON-80pq" and two HASH variants "Hash, Hasha". In this work an efficient programable hardware solution that supports all the three AEAD and two HASH variants is designed targeting GF12nm ASIC technology and Spartan-7 FPGA. The programmable design is compared to individual hardware implementations of each variant, demonstrating significant enhancements. By utilizing a single programmable design instead of five separate ones, 61% reduction in total silicon area and 75% energy savings are achieved. In addition, a comprehensive comparison of hardware implementations for each ASCON variant is provided. Performance metrics such as area, throughput, and energy consumption are evaluated, revealing that ASCON-128a offers the lowest energy consumption (0.45 pJ/bit) with the highest throughput (12.15 Gbps), while ASCON-128 achieves the smallest silicon footprint (1242 μm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> on GF12nm).