An Area-Efficient Readout Circuit for a High-SNR Triple-Gain LOFIC CMOS Image Sensor

A lateral overflow integration capacitor (LOFIC) CMOS image sensor (CIS) can achieve high-dynamic-range (HDR) imaging by combining a low conversion-gain (LCG) signal with a high conversion-gain (HCG) signal. However, the signal-to-noise ratio (SNR) drops at the switching point from HCG to LCG due to the large pixel noise in the LCG signal. To address this issue, a triple-gain LOFIC-CIS with a middle conversion-gain (MCG) signal is introduced. In this paper, we propose an area-efficient readout circuit for the triple-gain LOFIC-CIS, utilizing amplifier-sharing and capacitor-sharing techniques to process the HCG, MCG, and LCG signals. A test chip of the readout circuit was fabricated using the 0.18 µm CMOS process, with an area overhead of only 7.6% and an SNR drop improvement of 8.05 dB compared to the readout circuit for a double-gain LOFIC-CIS.