A 1Mb RRAM Macro with Bipolar Forming for Improved Programming Yield and Cell-by-cell Write Verification Scheme
Resistive RAM(RRAM) has emerged as a promising candidate for the next generation non-volatile memories (NVMs) due to its low write voltage, compact area, and CMOS compatibility. In this work, we propose a 1Mb RRAM macro with bipolar forming to reduce the forming voltage and improve the programming yield. Additionally, a cell-by-cell write verification scheme is introduced to protect RRAM cells from overstress and improve RRAM yield. The test chip, fabricated using 40nm CMOS technology, occupies a core area of 2.34 mm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup>.
Authors
- Junjie Mu (ORCID: https://orcid.org/0000-0002-6496-6539)
- Wen Siang Lew (ORCID: https://orcid.org/0000-0002-5161-741X)
- Putu Andhita Dananjaya (ORCID: https://orcid.org/0000-0001-9416-6455)
- Byung-Kwon An
- Weng Hong Lai
- Tony Tae-Hyoung Kim (ORCID: https://orcid.org/0000-0002-1779-1799)
Institutions
- Nanyang Technological University (SG)
Publication Details
- Published
- 2025-05-25
- DOI
- https://doi.org/10.1109/iscas56072.2025.11043651
- Primary Topic
- Ferroelectric and Negative Capacitance Devices
- Type
- article
- Field-Weighted Citation Impact
- 0.00
Funders
- Ministry of Education