A CMOS Power-Efficient Continuous-Time Delta-Sigma Resistor-to-Digital Converter for Force-Sensing Applications

This paper presents an energy-efficient resistor-to-digital converter (RDC) to detect a wide resistance range force sensing resistor (FSR). The proposed RDC leverages a delta-sigma architecture, enabling a high linear readout range while maintaining excellent power efficiency. The design was fabricated in a 0.18-μm CMOS process. The SNDR of the design achieves 75.3 dB with a rapid measurement time of 0.17 ms while consuming only 42.78 μW. The energy efficiency figure of merit (FoM) is 1.54 pJ per measurement, and the architecture maintains 0.999 R<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> linearity in the resistance measurement range from 6.8 kΩ to 2.2 MΩ. The chip area is 2 mm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup>.