HLS Learning Approach: Efficient Optimization with Instruction Block Diagram

High-Level Synthesis (HLS) is a common approach for programming Field Programmable Gate Arrays (FPGAs) across various applications. HLS tools enable novice hardware designers to synthesize Register Transfer Level (RTL) representations from high-level software programming languages. However, adhering to a specific coding style and understanding the performance disparities post-synthesis can challenge new HLS users. This work introduces an Instruction Block Diagram (IBD) framework using inputs from the Vitis HLS Schedule Viewer to enhance the understanding of HLS compiler interpretation for the user code and guide optimization to improve efficiency.