In-Memory Logic Synthesis Methods based on Read Decoupled 8T and Transpose 11T SRAMs

In-memory computing (IMC) is regarded as the promising computer architecture to break through the von-Neumann bottleneck. Some in-memory logic operations, such as AND/NAND/OR/NOR/XOR, have been proposed to be implemented within SRAM array. However, the studies on the SRAM-based in-memory logic operations still focus on the gate-level. The implementation method of arbitrary logic functions is an open issue till now. In order to address this problem, this paper proposes the general in-memory logic synthesis methods based on the read decoupled 8T SRAM array and the transpose 11T SRAM array. The proposed synthesis methods are applied to some MCNC benchmark circuits. The synthesis results show that the in-memory logic circuit generated by the 8T SRAM array consumes smaller sub-array size, and the in-memory logic circuit generated by the 11T SRAM array consumes less compute cycles.