Verilog-A modeling of Floating-Gate (FG)-based Multiple-Input Translinear Elements

Multiple-input translinear Elements (MITEs) employing Floating Gate (FG) transistors are crucial for low-power analog signal processing due to their multiple-input capabilities. Traditionally, FG-based MITE circuits are designed using hand calculations and physically calibrated post-fabrication. This work introduces a Verilog-A model for FG-based MITEs, derived from empirical data measured from MITE devices on 350nm CMOS process, to enable advanced pre-silicon design and validation. The model facilitates the development of MITE-based circuits capable of performing analog multiplication and division. This approach enhances the design process by enabling simulations before fabrication and contributes to more efficient and versatile low-power analog circuit designs. Further, it allows designers to validate the design despite mismatches and variations.