Efficient Double-tail Dynamic Comparator Circuit for High-performance Analog-to-Digital Data Converters

This paper presents the circuit design of a two-stage dynamic comparator optimized for high-speed, high-resolution analog-to-digital converters (ADCs). A conventional double-tail comparator is used as a reference for benchmarking. The proposed comparator is implemented using a 28 nm CMOS process and simulated using the Spectre circuit simulator under a 1 V supply. Theoretical analysis and simulation results prove that the proposed circuit is faster compared to the conventional double-tail comparator, while mantaining the same power consumption. Additionally, the design exhibits reduced noise levels, with an RMS noise voltage of less than 100 μV, making it suitable for low-noise applications. In terms of the Figure-of-Merit (FoM), the proposed comparator achieves 128 μW mV<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> GHz<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">−1</sup>, showing a competitive performance compared to other state-of-the-art designs in the literature. These results highlight the effectiveness of the proposed comparator in applications requiring high-speed, low-power, and low-noise ADCs in advanced CMOS technology nodes.