A Hybrid All-NMOS Rectifier With Gate-Biasing Techniques Achieving a 22.3 dB Power Dynamic Range

This paper presents a hybrid all-NMOS rectifier with two gate-biasing techniques to extend the power dynamic range (PDR) for wireless power transfer. The proposed hybrid rectifier combines the strengths of the cross-connected (CC) and diode-based (DB) configurations, achieving both a high forward current and a small reverse current along the PDR. Additionally, two separate gate-biasing techniques are employed to optimize the gate bias voltage for the gate-biased-CC and gate-biased-DB parts, respectively. All transistors in the rectifier are NMOS transistors, which can minimize the total area when extended to multi-stage configurations. The circuit is implemented in a 180-nm CMOS process, occupying an area of 0.195 mm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup>. Experimental results show a sensitivity of -10.3 dBm with a 1 MΩ load and a peak power conversion efficiency of 78.6% at -7.4 dBm with a 3 kΩ load. In addition, the proposed rectifier achieves a PDR greater than 22.3 dB with loads below 5 kΩ.