A High-Gain Three-Stage Auto-Zeroing Residual Amplifier for High-Precision Pipelined SAR ADC

This paper proposes a residual amplifier (RA) with high open-loop gain, wide output swing, and integrated auto-zeroing (AZ) functionality. To satisfy the stringent relative gain error requirements of high-precision successive-approximation-register (SAR) analog-to-digital converters (ADCs), the RA employs a three-stage architecture to achieve enhanced open-loop gain while maintaining a broad output voltage range. Stability in the multi-stage design is ensured through the strategic placement of the second and third poles using the complex-pole method. The input stage incorporates a current-reuse technique to double the effective trans-conductance, reducing thermal noise and extending bandwidth without increasing static power consumption. Additionally, an AZ technique is integrated to suppress offset voltage and mitigate low-frequency 1/f noise. Simulated in a 40nm CMOS process, the opamp achieves an open-loop gain exceeding 130dB, and a loop gain of over 101 dB when configured as 61.5× switched-capacitor (SC) RA. The design delivers a bandwidth of 30 MHz, a phase margin greater than 60°, and an input-reference total noise of 14.8 μVrms, with a power consumption of 5.6 mW. These results demonstrate the RA’s capability to meet the demands of high-resolution pipelined SAR ADCs, combining precision, dynamic performance, and power efficiency.