Penta Interlocking Dual Ports 14T SRAM with Inside-Bit interleaving Layout Isolation for Soft Error Recovery

SRAM suffers from single event upset (SEU) and single event transient (SET) in harsh radiation environments. In this paper, a Penta Interlocking Dual Ports 14T (PIDP-14T) SRAM cell is proposed to improve cell stability. The PIDP-14T has the immunity of single node upset (SNU), multiple node upsets (MNU) and specific triple node upset (TNU). An inside-bit interleaving layout isolation method increases the distance of nearest sensitive nodes to 2.409 µm. Additionally, as SET in peripheral circuit results in half-select disturbance during the operation cycle, this paper introduced double module redundant (DMR) hardened decoding circuit to remove SET. The simulation results show that the cell can recover from special MNU of which the critical charge is almost 4 times of other cells, and the dual gate cell with DMR hardened decoding array are robust to write disturbance caused by SET.