Incremental Delta-Sigma ADC with Reduced Conversion Cycles via Quantization-Skip

This paper presents a technique to effectively reduce the number of conversion cycles of the 1<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">st</sup>-order incremental delta-sigma data converter (IADC1). Typically, an IADC1 requires 2<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">N</sup> cycles to achieve N-bit resolution if using a sinc<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1</sup> filter for reconstruction. The proposed quantization-skip technique can effectively reduce the average conversion cycles and, therefore, the energy consumption of an IADC1. Specifically, during conversion, the quantizer output is predicted using the previous bitstream pattern to achieve automatic bitstream fill-in without analog domain operations. Behavioral level simulations show that this technique can reduce the conversion cycles by 24% on average (maximum reduction of ~50%) with little digital overhead.