A 40 Gb/s Adaptive CTLE Using a Sub-Sampled PAM-4 Clock Recovery Circuit in 65nm CMOS

This brief introduces an adaptive continuous-time linear equalizer (CTLE) featuring a sub-sampled delay-locked loop (DLL) based clock recovery circuit. This circuit incorporates an inverse bang-bang phase detector (PD) that samples data at a one-sixteenth rate. A digitally tunable, inverter-based multiphase clock generator produces three clock phases for PD operation. The early and late signals from the PD output are used to estimate the eye opening of the incoming 4-level pulse amplitude modulation (PAM-4) data. Our adaptive algorithm utilizes the averaged early/late signals to digitally tune CTLE parameters, such as degeneration resistance and capacitance. The prototype chip, integrating both the CTLE and clock recovery circuit, is implemented in a 65 nm CMOS process. Post-layout simulations indicate a combined power consumption of 46.8 mW for the CTLE and clock recovery circuit at 40 Gb/s, achieving an energy efficiency of 1.17 pJ/b.