C-Arch: Chained Architecture towards Foundation Modeling of CMOS/FinFET Circuit Designs

Modeling process, operating condition, reliability, and technological variation in transistor level design introduce significant variance in device and performance parameters. This paper presents a machine-learning-based architectural approach that enhances model performance, as a step towards developing Foundation Models tailored for circuit data, accurately capturing technology and process-induced variations in leakage power, voltage, and current. The architecture incorporates the impact of varying operating conditions, including temperatures from -55°C to 125°C and supply voltage fluctuations of ±10% on 16nm HP FinFET, and 16nm, 22nm, 32nm, and 45nm HP-MGK CMOS technology nodes. By enhancing the performance of baseline machine-learning models using a chained architecture to cater to the high variance in target, our C-Arch serves as a versatile framework for circuit modeling when the data spread is high. Experimental results on current, voltage, and leakage power estimation, demonstrate average improvements of up to 93.76%, 96.17%, and 88.82% in Mean Absolute Percentage Error compared to baseline models, underscoring the computational savings and viability of Foundation Models in circuit design.