A Deep Learning Accelerator for Modified YOLOv7-tiny with Shortcut-Aware Layer Fusion

Convolutional Neural Networks (CNNs) have become dominant in object detection tasks. However, off-chip data traffic, primarily from intermediate feature maps, remains a major performance bottleneck in CNN accelerators. This paper proposes a deep learning accelerator for YOLOv7-tiny with the following features: 1) A Shortcut-Aware Layer Fusion method that reduces off-chip feature map traffic by 32%. 2) A Multi-Bank Memory Control Scheme that efficiently manages all feature map data in one unified on-chip buffer, eliminating unnecessary data copying and improving the utilization of buffer resources. The design is implemented in TSMC 28 nm HPC+ process and occupies 2.19 mm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup>. The proposed accelerator achieves an energy efficiency of 3.0 TOPS/W and processes 640×640 input images at 34.5 FPS.

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Publication Details

Published
2025-05-25
DOI
https://doi.org/10.1109/iscas56072.2025.11043183
Citations
1
Primary Topic
Infrared Target Detection Methodologies
Type
article
Field-Weighted Citation Impact
4.99
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article

A Deep Learning Accelerator for Modified YOLOv7-tiny with Shortcut-Aware Layer Fusion

Shyh‐Jye Jou, Wei-En Huang, Yi-Shan Huang
1 citations
Infrared Target Detection Methodologies
4.99
article

A Deep Learning Accelerator for Modified YOLOv7-tiny with Shortcut-Aware Layer Fusion

Shyh‐Jye Jou, Wei-En Huang, Yi-Shan Huang
article en
1 citations

Abstract

Convolutional Neural Networks (CNNs) have become dominant in object detection tasks. However, off-chip data traffic, primarily from intermediate feature maps, remains a major performance bottleneck in CNN accelerators. This paper proposes a deep learning accelerator for YOLOv7-tiny with the following features: 1) A Shortcut-Aware Layer Fusion method that reduces off-chip feature map traffic by 32%. 2) A Multi-Bank Memory Control Scheme that efficiently manages all feature map data in one unified on-chip buffer, eliminating unnecessary data copying and improving the utilization of buffer resources. The design is implemented in TSMC 28 nm HPC+ process and occupies 2.19 mm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup>. The proposed accelerator achieves an energy efficiency of 3.0 TOPS/W and processes 640×640 input images at 34.5 FPS.

National Yang Ming Chiao Tung University (TW)
Openalex Percentile: Top 6%
Infrared Target Detection Methodologies
4.99
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A Deep Learning Accelerator for Modified YOLOv7-tiny with Shortcut-Aware Layer Fusion — Shyh‐Jye Jou, Wei-En Huang, et al. · (2025) | TGRS Research Map | TGRS