A Refresh-Reduction Digital eDRAM CIM Macro using Asymmetric Error Tolerance Scheme

In this work, we propose a refresh-reduction 3T1C eDRAM-based digital Compute-In-Memory (CIM) macro with an asymmetric error tolerance scheme to improve the energy consumption caused by frequent refresh operations. The novel asymmetric error tolerance scheme is first implemented in an eDRAM-based CIM macro to mitigate the effects of the wrong weights, extending the refresh period of the eDRAM cell. 3T1C eDRAM cell exhibits precise asymmetric error behavior, perfectly adapting the proposed asymmetric error tolerance scheme. Additionally, a reconfigurable refresh controller is introduced to eliminate refresh performance overhead during CIM operations and further reduce power consumption by reusing CIM readout data. The proposed 128Kb eDRAM-based CIM macro, simulated at 28nm, achieves a 98-100% improvement in the refresh period and a 21.5% improvement in average energy efficiency at 25°C and 60°C.