CMOS Ring Oscillator Ising Machine Using Sub-harmonic Injection Locking

Ising machines model nature dynamics to solve nondeterministic polynomial time (NP) hard combinatorial optimization problems (COPs). Because physical systems can naturally minimize their energy, these Ising machines have higher efficiency as compared to von Neumann architectures. This makes Ising machines attractive for tackling complex optimization problems mapped to the Ising Hamiltonian. In this paper, a highly scalable CMOS-compatible Ising machine design is proposed that leverages ring oscillator coupling under second-order sub-harmonic injection locking (SHIL). The proposed design is smaller and faster as compared to the state-of-the-art based on initial findings. Unlike traditional designs that use external injection locking signals or bulky LC oscillators, the proposed approach integrates both spin representation and SHIL signal generation directly on-chip using lightweight ring oscillators. The phase readout process is simplified by utilizing XOR gates for efficient spin readout. The initial results, obtained through SPICE simulations on 28nm FDSOI technology, confirm the feasibility of the proposed design. This approach presents a compact high-speed Ising machine with potential applications in solving a wide range of NP-hard problems.