A 0.9 V Configurable Dual Mode Comparator using a Supply Boosting Technique

High-speed dynamic latch comparators are integral part of the state-of-the-art ADCs. This work presents a configurable dual-mode voltage comparator using a supply boosting technique. The power dissipation of the comparator is proportional to the square of the supply voltage. Hence, the comparator is configured to operate at a supply voltage of 0.9 V under normal operating conditions. During high-performance mode, when the input differential voltage is small, the supply voltage is boosted to 1.5 V, satisfying the power-delay trade-off. The architecture is designed and simulated in a 180-nm CMOS technology with a supply voltage of 0.9 V. The increased supply voltage of 1.5 V is generated internally using a switched capacitor technique. The power consumed at 0.9 V and 1.5 V is 0.4 mW and 1.29 mW, respectively. The simulated offset at ΔV<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">IN</inf> = 1 mV in Mode = 0 and Mode = 1 turns out to be 4.05 mV and 3.14 mV respectively.