A 600-pW, 34.6 ppm/°C, -50 °C to 130 °C CMOS Voltage Reference with Leakage-Based Temperature Compensation and Supply Rejection Enhancement Techniques

This paper presents a sub-1V output voltage reference circuit using a 0.18-μm CMOS technology. The circuit uses a stacked-diode-MOS-transistor (SDMT) architecture, which ensures excellent supply and temperature independence at low power consumption. Additionally, leakage-based temperature compensation allows for an expanded operating temperature range, while frequency compensation techniques extend the bandwidth of supply rejection. The design achieves a temperature coefficient of 34.6 ppm/°C over a range of -50 to 130 °C, a line sensitivity of 0.014 %/V, and a power supply rejection ratio of -67 dB at 100 Hz. The circuit consumes only 600 pW of power and takes up a chip area of 0.0079 mm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup>.