A Design Study of Power-Efficient Opamp Topologies for Discrete-Time ∆Σ Modulators

The design of ultra-low power, highly linear and low noise Delta-Sigma modulators (DSMs) is an active topic in research and industrial application to realize high-resolution analog-to-digital converters (ADCs) for applications such as audio, sensor or IoT digitization. In such DSMs, the first integrator stage usually consumes most of the power, which is why innovative amplifier architectures have been proposed. This paper presents a case study of different state of the art power-efficient operational amplifier (OpAmp) topologies in a 180 nm CMOS technology using a standard 1.8V supply. A detailed comparison is made in terms of power, noise, area, linearity, and design effort, which can serve as a guide for designers when choosing the most suitable amplifier architecture for such application.